In the manufacture of integrated circuits, interconnects can be formed on a semiconductor substrate, often using a dual damascene process. Such a process begins with a trench formed in a dielectric layer over which various layers such as an adhesive layer, a barrier layer, and other layers such as a seed layer may be subsequently formed. The adhesion layer is used because the subsequently deposited metals do not readily nucleate on barriers. The barrier layer prevents a copper (Cu) layer from diffusing into the underlying dielectric layer. This may be followed by an electroplating (EP) process used to deposit a bulk copper layer to fill the trench and form the interconnect.
Some manufacturing technologies use a physical vapor deposition (PVD) process to form barrier and Cu seed layers followed by EP Cu layer. As features continue to shrink, limited extendibility of a PVD seed layer may occur due to its non-conformal characteristics, which cause large overhang and incomplete sidewall coverage. Overhang decreases entrance opening and increases effective aspect ratio beyond the filling capabilities of current EP gapfill technology. Thus options for conformal, platable, barrier or liner layers are being pursued. Although barrier/liner layers do not typically have a passivation oxide layer, surface oxides are still present, preventing void-free Cu EP due to poor Cu nucleation. Thus, direct EP or electroless (EL) deposition of copper on a liner layer is difficult, due to presence of stable oxides, leading to poor nucleation and three dimensional (3D) rough microstructure, and EP voids within features.